LC01707PLF
Continued from preceding page.
Register
Read/
Binary
Hex
address
BIT
Bit name
Function
Bit operation
Write
value
value
20h
7
0
6
5
ERR2
ERR1
Local oscillator capacitor bank control error flag 2
Local oscillator capacitor bank control error flag 1
R/W
R/W
0
0
1:cap bank control value 0:I C input value
4
DCOSEL2
Local oscillator capacitor bank value changeover
2
R/W
0
3
DCOSEL1
Local oscillator capacitor bank control process
1:correcting process after sequential comparison
R/W
1
h’0A
changeover
0:No correcting process after sequential comparison
2
DCOSEL0
Local oscillator capacitor bank control process
1:micro adjustment process 0:No micro adjustment process
R/W
0
changeover (micro alignment)
1
0
DWAITSEL[1]
DWAITSEL[0]
PLL operation check wait time after local oscillator
capacitor bank adjustment
0:200 μ s 1: 400 μ s 2:800 μ s 3:1600 μ s
R/W
R/W
1
0
21h
7
6
0
0
5
4
DENINT
MASKSEL
Register for TEST
Register for TEST
R/W
R/W
0
0
h’0A
3
2
1
0
LOSEL
INTPH
INTIM
INTLO
Register for TEST
Register for TEST
Register for TEST
Register for TEST
R/W
R/W
R/W
R/W
1
0
1
0
22h
7
6
5
TESTSEL[2]
TESTSEL[1]
TESTSEL[0]
Register for TEST
Register for TEST
Register for TEST
R/W
R/W
R/W
0
0
0
4
DSW
PLL loop filter ON/OFF
1:ON 0:OFF
R/W
1
3
TIMESEL2[1]
Local oscillator capacitor bank control correcting circuit
operation clock setting
0:200 μ s 1: 400 μ s 2:800 μ s 3:1600 μ s
R/W
0
h’15
2
TIMESEL2[0]
R/W
1
1
0
TIMESEL[1]
TIMESEL[0]
Local oscillator capacitor bank control sequential
comparison control operation clock setting
0:10 μ s 1: 20 μ s 2:40 μ s 3:80 μ s
R/W
R/W
0
1
SD pin specification
SD voltage level VDD: supply voltage
High level output voltage
Low level output voltage
item
min
VDD-0.8
0
max
VDD
0.4
unit
V
V
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